ICP specifications?

Cockpit, radar, helmet-mounted display, and other avionics
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uclass

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Unread post10 Jul 2015, 17:13

Did a quick google and it returned this:

http://www2.l-3com.com/displays/pdfs/redesign/ICP(2011)_LR.pdf

Basically a small supercomputer.

TWO HIGH PERFORMANCE POWER
SUPPLIES
Input Power 28VDC 28VDC
Voltage Range 16-29 Volts 16-29 Volts
Transient Suppression Included Included
Power Dissipation 300 Watts (max.) 450 Watts (max.)
PHYSICAL DESCRIPTION
Weight 36 lbs 50 lbs (max.)
Dimensions 10.2”(w) x 7.6”(h) x 12.3”(d)
w/Fan Pack: 10.2”(w) x 7.6”(h) x 13.5”(d)
10.2”(w) x 7.6”(h) x 19”(d)
w/Fan Pack: 10.2”(w) x 7.6”(h) x 19.6”(d)
ENVIRONMENTAL PERFORMANCE
Temperature Operating: -40°C to +55°C, +71°C (intm.)
Storage: -57°C to +85°C
Operating: -40°C to +55°C, +71°C (intm.)
Storage: -57°C to +85°C
Shock 20 Gs (basic), 40 Gs (crash) 20 Gs (basic), 40 Gs (crash)
Altitude 0-50,000 ft 0-50,000 ft
Reliability 7,000 hours (AIC) 5,000 hours (AIC)
EMI/EMC MIL-STD-460, CE102, CS101, 114-116,
KE102-103, RS103, lightning
MIL-STD-460, CE102, CS101, 114-116,
KE102-103, RS103, lightning
PROCESSING
CPU Up to 2 System Processor/Display
Processor Modules:
• System Processor:
» >2900 DMIPS, 1MB L2 Cache
» 512MB DRAM, 256MB Flash
» 128KB NOVRAM
• Display Processor:
» >2200 DMIPS, 1MB L2 Cache
» 256MB DRAM, 128MB Flash
Up to 3 System Processor/Display
Processor Modules:
• System Processor:
» >2900 DMIPS, 1MB L2 Cache
» 512MB DRAM, 256MB Flash
» 128KB NOVRAM
• Display Processor:
» >2200 DMIPS, 1MB L2 Cache
» 256MB DRAM, 128MB Flash
Video / Graphics Up to 2 Video/Graphics Processors:
• Supports graphics only, video only,
graphics overlay on video
• Supports standard PC video & HDTV
formats up to 2560x1600
Up to 4 Video/Graphics Processors:
• Supports graphics only, video only,
graphics overlay on video
• Supports standard PC video & HDTV
formats up to 2560x1600
SOFTWARE
Operating System Green Hills® INTEGRITY®-178B / MILS Green Hills® INTEGRITY®-178B / MILS
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Unread post14 Jul 2015, 18:05

You'll have to C&P the link, because it won't link the last bit for some reason. Ah fixed.

http://www2.l-3com.com/displays/pdfs/redesign/ICP(2011)_LR.pdf
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Dragon029

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Unread post14 Jul 2015, 19:24

It's pretty hard for me to compare it's processing power because they quote it in DMIPS (something normally used for niche application microprocessors) and obviously because it's optimised for a specific task, but as far as I can tell, it's roughly as fast as an Intel consumer processor from something like 2004. Still, that's a fairly apples and oranges comparison - good luck trying to get a computer from 2004 to run a 2560x1600 display. And as otherwise mentioned, each ICP runs only one of the 2 displays that make up the F-35's PCD.

Lastly, I'm not entirely sure what other processing (if any; other than GUI stuff) is done on these ICPs, but AFAIK you would also have a lot of processing related to data fusion happening in individual sensor systems - for example, having the computers in the AN/APG-81 performing the waveform analysis and cross-referencing signals against signatures in the F-35's threat library.
Last edited by Dragon029 on 14 Jul 2015, 21:44, edited 1 time in total.
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Unread post14 Jul 2015, 21:37

IIRC, These are only the ICPs related to the display and do not do any "sensor fusion".

That is handled by the ICPs in the weapon's bay.

--Update
Harris.com makes the main ICP and the radar rack too.
"The early bird gets the worm but the second mouse gets the cheese."
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geforcerfx

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Unread post14 Jul 2015, 23:53

Dragon029 wrote:It's pretty hard for me to compare it's processing power because they quote it in DMIPS (something normally used for niche application microprocessors) and obviously because it's optimised for a specific task, but as far as I can tell, it's roughly as fast as an Intel consumer processor from something like 2004. Still, that's a fairly apples and oranges comparison - good luck trying to get a computer from 2004 to run a 2560x1600 display. And as otherwise mentioned, each ICP runs only one of the 2 displays that make up the F-35's PCD.

Lastly, I'm not entirely sure what other processing (if any; other than GUI stuff) is done on these ICPs, but AFAIK you would also have a lot of processing related to data fusion happening in individual sensor systems - for example, having the computers in the AN/APG-81 performing the waveform analysis and cross-referencing signals against signatures in the F-35's threat library.


my inspiron xps from 2005 could do 2560 x1600 on my friends monitor, the systems main display was 1920 x 1200. We could even game on his monitor with the mobility radeon 9800.
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Unread post17 Jul 2015, 10:48

So I found out that the processing uses RACE++ hardware.

http://embeddedstar.com/press/content/2 ... 12722.html

2/5/2004 - Mercury Computer Systems, Inc. (NASDAQ: MRCY) announced that Raytheon Company (NYSE: RTN) has licensed its RACE++® Series multicomputers for use in the Integrated Core Processing (ICP) system of the F-35 Joint Strike Fighter (JSF).


This looks fairly close to the L-3 specs above?? Seems like there's more than one CPU per slot module.

https://www.mrcy.com/products/boards/race_powerpc7448/

The RACE++® Series PowerPC® 7448 Multicomputer is a high-performance drop-in product upgrade that adds significant improvements in processor speed, L2 cache size, memory available per processor, and application performance over the PowerPC MPC7447A. By maintaining commonality with previous RACE++ Series PowerPC products, Mercury provides an easy upgrade path for existing system designs.
The PowerPC 7448 Multicomputer is available in 6U and 9U form factors.

6U Form Factor
MCJ6 motherboard and two daughtercards.
Each daughtercard with either two 1.06-GHz MPC7448 processors or two 1.267-GHz processors with AltiVec™ technology.
MCJ6 configurations with one PowerPC 7448 daughtercard and one RINOJ-F-2.5 are also available

9U Form Factor
Up to seven PowerPC 7448 daughtercards and one RINOJ-F-2.5 available

PowerPC 7448 Daughtercard
For 1.06-GHzRACEway ports: 2
Processor frequency: 1.06-GHz
Compute nodes: 2
Memory frequency: 133 MHz
DDR DRAM per CN: 512 MB or 1024
DDR DRAM per daughtercard: 1024 MB or 2048 MB
L2 cache frequency: 1.06-GHz (32 bytes wide)
L2 on-chip cache: 1024 KB per CN

For 1.267-GHz
RACEway ports: 2
Processor frequency: 1.267-GHz
Compute nodes: 2
Memory frequency: 133 MHz
DDR DRAM per CN: 512 MB or 1024 MB
DDR DRAM per daughtecard: 1024 MB or 2048 MB
L2 cache frequency: 1.267-GHz (32 bytes wide)
L2 on-chip cache: 1024 KB per CN


And some of their stuff is scary for future upgrades :mrgreen: :

https://www.mrcy.com/products/ensemble- ... vancedtca/

https://www.mrcy.com/products/boards/En ... PU_Module/
Last edited by uclass on 17 Jul 2015, 13:50, edited 5 times in total.
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uclass

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Unread post17 Jul 2015, 10:57

Dragon029 wrote:It's pretty hard for me to compare it's processing power because they quote it in DMIPS (something normally used for niche application microprocessors) and obviously because it's optimised for a specific task, but as far as I can tell, it's roughly as fast as an Intel consumer processor from something like 2004. Still, that's a fairly apples and oranges comparison - good luck trying to get a computer from 2004 to run a 2560x1600 display. And as otherwise mentioned, each ICP runs only one of the 2 displays that make up the F-35's PCD.

Lastly, I'm not entirely sure what other processing (if any; other than GUI stuff) is done on these ICPs, but AFAIK you would also have a lot of processing related to data fusion happening in individual sensor systems - for example, having the computers in the AN/APG-81 performing the waveform analysis and cross-referencing signals against signatures in the F-35's threat library.

According to this, DMIPS are more representative of actual performance than MIPS, which include the execution of instructions that don't go anywhere.

https://en.wikipedia.org/wiki/Dhrystone
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geforcerfx

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Unread post18 Jul 2015, 04:57



I doubt they would move to x86(intel), I would bet any future computer upgrades will be ARM based so they stay with the RISC architecture.
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Unread post18 Jul 2015, 07:11

geforcerfx wrote:


I doubt they would move to x86(intel), I would bet any future computer upgrades will be ARM based so they stay with the RISC architecture.

Its unlikely they'll go to Intel x86 processors. PowerPC processors work with AMD GPUs just fine in other applications. For the F-35, Its possible they'll adopt a hybrid approach, with the FPGAs running a "soft core" coupled to GPUs.

The problem is that legacy mission systems code is hard to port to completely different architectures. Even ARM-based processors would be a stretch. One likely future possibility is that they'll use a FPGA "soft" PowerPC core along with accelerator cores for DSP and sensor fusion graphics displays.

In the F-22, the Central Integrated Processor originally used i960 processor cores. Even though the upgraded CIP uses PowerPC processors, they also use FPGAs to provide soft i960 processors for compatibility with legacy code.

What most people don't realize is that military flight simulators were one of the first applications of computer graphics rendering. Companies like SGI made workstations that were at least 10 years ahead of the mainstream PC. Even a 2005 high-end mobile workstation class laptop could probably handle the F-35 cockpit display. The F-35 display doesn't use a high color depth or "texture" resolution compared to a rendering a CAD visualization or CGI scene.

GPGPU is great for some applications, although its basically putting a round peg in a square hole. The GPU is designed for graphics, not general purpose computing. When component cost is not major factor and legacy architecture compatibility is a major factor, FPGAs are used. The computing power and signal processing capability of a high-end FPGA is amazing and its likely that 20 years in the future, newer FPGAs with will provide upgraded capabilities in a legacy airframe.

Future avionics will migrate towards neural network processors, that are nothing like regular RISC architectures.
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Unread post18 Jul 2015, 08:26

The GPUs would probably take away the strain by handling graphics and I'm fairly sure they handle maths operations too, being widely used in super computing, the Nvidia Tesla being a popular example.

http://www.nvidia.com/object/tesla-servers.html

I imagine there's actually a lot of graphic and raw maths processing one way or another in sensor data processing and fusion, e.g. identifying objects on EODAS/EOTS/Radar/SAR via shape, geolocation calculations, speed, range and bearing calculations. Combing two positional fixes from separate sensors to give a more accurate fix. Relaying EODAS and other imagery to the HMD etc.
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Unread post25 Oct 2015, 10:28

Okay, following on from above, I found more information:

http://embeddedstar.com/press/content/2 ... 12722.html

Raytheon Selects RACE++ Multicomputers for F-35 Joint Strike Fighter


http://www.freescale.com/files/32bit/do ... 48FACT.pdf

Superscaler Core
The MPC7448 processor features a
high-frequency superscalar e600 PowerPC
core*, capable of issuing four instructions per
clock cycle (three instructions plus one
branch) into
11 independent execution units:
> Four integer units (three simple plus one
complex)
> Double-precision floating point unit
> Four AltiVec technology units (simple,
complex, floating and permute)
> Load/store unit
> Branch processing unit
AltiVec Acceleration
The MPC7448 includes the same powerful
128-bit AltiVec vector execution unit as found
in previous MPC7xxx devices. AltiVec
technology may dramatically enhance the
performance of applications such as voiceover-Internet
Protocol (VoIP), speech
recognition, multi-channel modems, virtual
private network servers, high-resolution 3-D
graphics, motion video (MPEG-2, MPEG-4),
high fidelity audio (3-D audio, AC-3), and so
on. AltiVec computational instructions are
executed in the four independent, pipelined
AltiVec execution units. A maximum of two
AltiVec instructions can be issued in order to
any combination of AltiVec execution units per
clock cycle. In the MPC7448, a maximum of
two AltiVec instructions can be issued out-oforder
to any combination of AltiVec execution
units per clock cycle from the bottom two
AltiVec instruction queue entries. For example,
an instruction in queue one destined for
AltiVec integer unit one does not have to wait
for an instruction in queue zero that is stalled
behind an instruction waiting for operand
availability


So it looks like each of the modules described in http://www2.l-3com.com/displays/pdfs/redesign/ICP(2011)_LR.pdf has 7 daughter cards with 2 of these 7448 procesors.
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Unread post25 Oct 2015, 16:00

http://www.aviationtoday.com/av/militar ... iztOrfhCUk

Core Processor
Hosting the mission systems software is the JSF's electronic brain, the ICP. Packaged in two racks, with 23 and eight slots, respectively, this computer consolidates functions previously managed by separate mission and weapons computers, and dedicated signal processors. At initial operational capability, the ICP data processors will crunch data at 40.8 billion operations/ sec (giga operations, or GOPS); the signal processors, at 75.6 billion floating point operations (gigaflops, or GFLOPS); and the image processors at 225.6 billion multiply/accumulate operations, or GMACS, a specialized signal processing measure, reports Chuck Wilcox, Lockheed's ICP team lead. The design includes 22 modules of seven types:

Four general-purpose (GP) processing modules,
Two GPIO (input/output) modules,
Two signal processing (SP) modules,
Five SPIO modules,
Two image processor modules,
Two switch modules, and
Five power supply modules.

The ICP also will have� "pluggable growth" for eight more digital processing modules and an additional power supply, Wilcox adds. It uses commercial off-the-shelf (COTS) components, standardizing at this stage on Motorola G4 PowerPC microprocessors, which incorporate 128-bit AltiVec technology. The image processor uses commercial field programmable gate arrays (FPGAs) and the VHDL hardware description language to form a very specialized processing engine.The ICP employs the Green Hills Software Integrity commercial real-time operating system (RTOS) for data processing and Mercury Computer Systems' commercial Multi-computing OS (MCOS) for signal processing. Depending on processing trades still to be made in the program, the JSF also could use commercial RTOSs in sensor front ends to perform digital preprocessing, according to Baker. The display management computer and the CNI system also use the Integrity RTOS. COTS reduces development risk and� ensures an upgrade path, according to Ralph Lachenmaier, the program office's ICP and common components lead.

Tying the ICP modules together like a backplane bus and connecting the sensors, CNI and the displays to the ICP is the optical Fibre Channel network. Key to this interconnect are the two 32-port ICP switch modules. The 400-megabit/sec IEEE 1394B (Firewire) interconnect is used externally to link the ICP, display management computer and the CNI system to the vehicle management system.
Low-level processing will occur in the sensor systems, but most digital processing will occur in the ICP. The radar, for example, will have the smarts to generate waveforms and do analog-to-digital conversion. But the radar will send target range and bearing data to the ICP signal processor, which will generate a report for the data processor, responsible for data fusion. Radar data, fused with data from other onboard and offboard systems, then will be sent from the ICP to the display processor for presentation on the head-down and helmet-mounted displays.
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Unread post25 Oct 2015, 16:28

So one breakpoint to crash the whole system?
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Unread post25 Oct 2015, 16:46

I'd bet on it being multiplexed.
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Unread post25 Oct 2015, 17:39

For the sake of following up on the AVIONICS story above then it has been mentioned (about the display) here:

viewtopic.php?f=62&t=16223&p=215234&hilit=Charlotte#p215234

Then in full here wayback in 2004 by 'bring_it_on1' : viewtopic.php?f=60&t=847&p=10332&hilit=Charlotte#p10332

Why? Because there may be other useful information at the internal links above also.
A4G Skyhawk: www.faaaa.asn.au/spazsinbad-a4g/ & www.youtube.com/channel/UCwqC_s6gcCVvG7NOge3qfAQ/videos?view_as=subscriber

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